Programmable logic arrays are well known in the art. Generally, a programmable logic array consists of a first array of AND gates having their inputs programmably coupled to input terminals of the logic array chip. The outputs of the various AND gates forming the AND array are coupled, either programmably or nonprogrammably, to inputs of an OR array. The outputs of the OR array are then coupled to output terminals of the logic array chip so that a signal provided at an output terminal may be a sum of a product of a plurality of input signals applied to the input terminals of the chip. An extremely wide variety of logic functions may be obtained with this generic type of programmable logic array circuit. On such programmable logic array circuit is described in U.S. Pat. No. 4,124,899, issued to Birkner et al., incorporated herein by reference.
A modification of the basic programmable logic array design described in U.S. Pat. No. 4,124,899 is the Gazelle Microcircuit, Inc. Model GA23SV8 programmable logic array sequencer, described in the GA23SV8 data book (April 1989), incorporated herein by reference. This sequencer uses what is known in the art as buried registers, whose inputs are coupled to the outputs of an OR array and whose outputs are programmably coupled to the inputs of an AND array to provide an internal feedback path. In the Model GA23SV8 sequencer, these buried registers are D flip flops. Thus, the outputs of these buried registers are treated in the same way as input signals applied to the input terminals of the logic array chip.
Clocked output registers in the GA23SV8 sequencer are connected to receive an associated output signal from the OR array and output a signal through a buffer to an associated output terminal of the logic array chip. The output signal provided at the output terminals may also be fed back into the logic array and treated as an additional input signal into the AND array. In the GA23SV8 sequencer, these output registers are D flip flops.
One known application of buried and/or output registers is to configure them as a counter, where the logic array is programmed such that the output of one or more of the registers provides input signals to the AND array corresponding to the number of counting operations performed by the counter. For example, it may be desirable for an input signal to go high after eight counts. Accordingly, the logic array would be programmed for the registers to act as a binary counter, and outputs of the appropriate registers would be applied to the input of the AND array to signal the occurrence of every eighth count.
In the Model GA23SV8 sequencer and in the numerous other programmable logic device (PLD) products on the market, a common externally generated clock pulse is applied to all registers in the programmable logic array chip so that all the registers change states, or are otherwise updated, simultaneously.
One type of PLD which does not couple a single clock signal to all registers is the Model PAL20RA10 available from Advanced Micro Devices (AMD), Inc. In the Model PAL20RA10, each register has its clock input terminal connected to a separate output of a logic array to selectively control the timing of each register.
The maximum clocking rate of a register is the rate of an externally generated input signal applied to the clock input of the register through the logic array.
One circuit which uses a high speed internally generated clock signal to clock output registers is the Model Am2971 Programmable Event Generator (PEG) by AMD. The Model Am2971 uses a phase-locked loop (PLL) to generate a clock signal to clock output registers. The output registers are also used to feed back address signals into a programmable read only memory (PROM). The feedback signals are then decoded by the PROM, which applies the data contained in the address to the output registers. A portion of the data is provided to output terminals of the PEG, while a portion of the data is used as address signals to address data in the PROM. However, since the PROM is unable to generate a feedback signal for controlling the phase of the PLL used to clock the output registers, the output signals from the PROM are not synchronized with the externally generated clock reference signal applied to the PLL Thus, the Am2971 would not be well suited for applications where output signal transitions of the Am2971 must be synchronized with transitions of an externally generated reference signal.
Applicants have discovered a heretofore unsatisfied need in the art for a monolithic logic array circuit with the ability to clock internal registers using an internally generated clock signal. Prior art monolithic logic array circuits are unable to provide any of the numerous benefits, which will be discussed below, obtained by clocking registers at a rate faster than the externally generated clock pulse applied to the logic array chip.